How To Solve EMI Problem In Multilayer PCB Design?

- Jun 26, 2017-

  How to solve EMI problem in multilayer PCB design?

  There are many ways to solve EMI problem, modern EMI suppression methods include: using EMI to restrain coating, selecting suitable EMI Control parts and EMI simulation design. Based on the most basic PCB board, this paper discusses the function and design skills of PCB laminated stacking in the control of EMI radiation.

  Power bus

  In the IC's power pin near the reasonable placement capacity of the capacitance, can make the IC output voltage jumps faster.multilayer PCB However, this is not the end of the question. Due to the characteristic of a finite frequency response, the capacitance is not able to generate the harmonic power required for a clean drive IC output in the full frequency band. In addition, the transient voltage formed on the power bus is a voltage drop at both ends of the decoupling path, and these transient voltages are the main source of common-mode EMI interference. How should we solve these problems?

  As far as the IC on our circuit board plant is concerned, the power supply layer around the IC can be regarded as an excellent high-frequency capacitor,multilayer PCB which collects the part of the energy that is leaked for a discrete capacitor that provides high frequency energy for a clean output. In addition, the excellent power layer inductance to small, so that the inductor synthesized transient signal also small, and thus reduce the common mode EMI.

  Of course, the power layer to the IC power pins must be as short as possible, because the digital signal rising along more and more quickly, preferably directly connected to the IC power pin on the pad, this should be discussed separately.

  In order to control the common mode EMI, the power supply layer should be helpful to decoupling and have low inductance, this power layer must be a good design of the power layer pairing. One might ask, how good is it?multilayer PCB The answer to the question depends on the layering of the power, the material between the layers, and the operating frequency (that is, the function of the IC rise time). Typically, the spacing of power tiers is 6mil, and the interlayer is FR4 material, then the equivalent capacitance per square inch power supply layer is about 75pF. Obviously, the smaller the layer spacing, the greater the capacitance.

  The increase time is 100 to 300PS devices are not many, but according to the current IC development speed, the rise time in 100 to 300ps range of devices will occupy a high proportion. For circuits with a 100 to 300ps rise time, the 3mil layer spacing will no longer apply to most applications. At that time,multilayer PCB it is necessary to adopt layered technology with a layer spacing of less than 1mil, and replace FR4 dielectric materials with high dielectric constant. Now, ceramics and add-pottery plastic can meet the design requirements of the 100 to 300ps rise time circuit.

  Although new materials and methods may be used in the future, for today's common 1 to 3ns rise time circuit, 3 to 6mil layer spacing and FR4 dielectric materials, it is usually enough to handle high-end harmonics and make the transient signal low enough,multilayer PCB that is to say, common mode EMI can be lowered very low. This paper gives a layered stack design example of PCB board will assume that the layer spacing is 3 to 6mil.

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